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Honored Contributor

14 years ago

ModelSim -> Error: xxxxx.vhd(n): Library yyyy not found

I'm trying to run an RTL Simulation of a project using the NativeLink set-up in Quartus II. But I end up with the following error: (in red)

--- Quote Start ---

Reading C:/altera/11.0sp1/modelsim_ase/tcl/vsim/pref.tcl

# do GrabReader_run_msim_rtl_vhdl.do

# if {[file exists rtl_work]} {

# vdel -lib rtl_work -all

# }

# vlib rtl_work

# vmap work rtl_work

# Copying c:\altera\11.0sp1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini

# Modifying modelsim.ini

# ** Warning: Copied c:\altera\11.0sp1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.

# Updated modelsim.ini.

#

# vcom -93 -work work {C:/qdesigns/c-cam/bb/vhdl_packages/CC_Data_Types.vhd}

# Model Technology ModelSim ALTERA vcom 6.6d Compiler 2010.11 Nov 2 2010

# -- Loading package standard

# -- Loading package std_logic_1164

# -- Loading package numeric_std

# -- Loading package math_real

# -- Loading package lpm_components

# -- Compiling package cc_data_types

# -- Compiling package body cc_data_types

# -- Loading package cc_data_types

# vcom -93 -work work {C:/qdesigns/c-cam/bb/gates/regmux/regmux.vhd}

# Model Technology ModelSim ALTERA vcom 6.6d Compiler 2010.11 Nov 2 2010

# -- Loading package standard

# -- Loading package std_logic_1164

# -- Loading package lpm_components

# ** Error: C:/qdesigns/c-cam/bb/gates/regmux/regmux.vhd(7): Library cc_data_types not found.

# ** Error: C:/qdesigns/c-cam/bb/gates/regmux/regmux.vhd(8): (vcom-1136) Unknown identifier "cc_data_types".

# ** Error: C:/qdesigns/c-cam/bb/gates/regmux/regmux.vhd(11): VHDL Compiler exiting

# ** Error: c:/altera/11.0sp1/modelsim_ase/win32aloem/vcom failed.

# Error in macro ./GrabReader_run_msim_rtl_vhdl.do line 9

# c:/altera/11.0sp1/modelsim_ase/win32aloem/vcom failed.

# while executing

# "vcom -93 -work work {C:/qdesigns/c-cam/bb/gates/regmux/regmux.vhd}"

--- Quote End ---

So Modelsim doesn't seem to find a package in a lower module, although it had no problem locating it just a bit earlier.

If I run the Gate Level Simulation everything runs OK, except that I don't get a clock running.

	genclk : process
		begin
			Clk <= '0' ;
			wait for TClChClk ;
			Clk <= '1' ;
			wait for TClChClk ;
		end process genclk ;

For building Lower level modules a Gate Level Simulation is not really necessary, so I tried the RTL Simulaton.

Any clues?

21 Replies

Altera_Forum
Honored Contributor
14 years ago
The error:

Library cc_data_types not found.

can probably be resolved by

vmap cc_data_types rtl_work

I suspect that in the regmux code you have

library cc_data_types;
use cc_data_types.cc_data_types.all;

or something like that.

Modelsim is expecting to find these data types in that library, whereas your script compiles them into 'work'.

Alternatively you can

vlib cc_data_types
vmap cc_data_types cc_data_types
vcom -93 -work cc_data_types {C:/qdesigns/c-cam/bb/vhdl_packages/CC_Data_Types.vhd}

Or something pretty close to that ...

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
Hi Dave,

--- Quote Start ---
I suspect that in the regmux code you have

library cc_data_types;
use cc_data_types.cc_data_types.all;
--- Quote End ---

Spot on! It is in about every VHDL code I write nowadays. I have another package like that.

The idea was to have the 'NativeLink' do it all for me ... (kind of like the 'euthanized' Internal Quartus Simulator where one clicked Run Simulation and waited for the result waveform to show up)

Apart from that do you have a clue why I can't get the clock to work, Gate Simulation runs fine, i.e. ModelSim shows a waveform, but I don't see the generated Clk signal toggle at all.

Regards,

Josy
Altera_Forum
Honored Contributor
14 years ago
Hi Josy,

--- Quote Start ---

Spot on! It is in about every VHDL code I write nowadays. I have another package like that.

--- Quote End ---
It is good coding practice to use libraries. Modelsim is nice enough to allow precompiled libraries, so having 'library' code (stuff you do not touch once it is working) compiled into a library is nice, since it you do not need to recompile it.

--- Quote Start ---

The idea was to have the 'NativeLink' do it all for me ... (kind of like the 'euthanized' Internal Quartus Simulator where one clicked Run Simulation and waited for the result waveform to show up)

--- Quote End ---
I tend to treat Modelsim and Quartus as completely independent tools, and control each with Tcl scripts. I have never used Nativelink, and am unlikely to try it :)

--- Quote Start ---

Apart from that do you have a clue why I can't get the clock to work, Gate Simulation runs fine, i.e. ModelSim shows a waveform, but I don't see the generated Clk signal toggle at all.

--- Quote End ---
What is the variable getting set to? Try adding this code:

assert false report "Clock half period is " & time'image(TClChClk) severity note;
Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
Hi Dave,

Unfortunately I tend to 'augment' my main library on almost a daily basis. So it would be nice to automate ModelSim a bit.

--- Quote Start ---
I tend to treat Modelsim and Quartus as completely independent tools, and control each with Tcl scripts.
--- Quote End ---
I see the difference, but then I 'grew up' with MaxPlusII and Quartus, at first without the II and I have a hard time separating. The reflex still is to code in QuartUS II and run it through the internal simulator. But as you indicate I could easily write the (low-level) code in an external editor, e.g. Sigasi, use ModelSim to do the RTL-simulation, and later integrate it all in Quartus II or Qsys, and as I rarely simulate a top level file,as to my idea one shouldn't have to, I'd be finished.

I'll try the assertion later.

Regards,

Josy
Altera_Forum
Honored Contributor
14 years ago
Hi Josy,

--- Quote Start ---

Unfortunately I tend to 'augment' my main library on almost a daily basis. So it would be nice to automate ModelSim a bit.

--- Quote End ---
Tcl is definitely the way to go to automating Modelsim.

--- Quote Start ---

I 'grew up' with MaxPlusII and Quartus, at first without the II and I have a hard time separating.

--- Quote End ---
I did too. Having to manually create waveforms in the the Max+PlusII simulator led me to start using Modelsim.

I guess you were just more patient than me :)

--- Quote Start ---

But as you indicate I could easily write the (low-level) code in an external editor, e.g. Sigasi, use ModelSim to do the RTL-simulation, and later integrate it all in Quartus II or Qsys, and as I rarely simulate a top level file,as to my idea one shouldn't have to, I'd be finished.

--- Quote End ---
I create components in a lib/ folder. Each component has its own folder, and testbench. The testbench can be run via a 'make check' Makefile, so that if I edit a component and break others, I find out reasonably soon ('make check' is run on all testbenches in the lib/ folder). These components can then be used in higher level designs, eg., a Qsys system. I typically include an Avalon-MM BFM in those systems, and then write a basic testbench to check everything is working. All my lib/ code is in VHDL, whereas the Qsys stuff needs to use SystemVerilog ... so Modelsim full-edition is required. I'll write an Avalon-MM BFM in VHDL one of these days ...

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
Hi Dave,

--- Quote Start ---
I did too. Having to manually create waveforms in the the Max+PlusII simulator led me to start using Modelsim.

I guess you were just more patient than me
--- Quote End ---

I ran my first successful ModelSim simulation yesterday (on a lazy Sunday afternoon ...) and you are quite right (as usual) generating repetitive signals is quite easy and very neat.

I used the native link in QII and that runs fine. Today I decided to continue on the momentum and tried to simulate the other part of the project. So I went through exactly the same motions, copy-paste-edited some of the first testbench into the second. Started the (gate-level) simulation but got this error:

--- Quote Start ---
# ** Error: (vsim-13) Recompile work.iddramread because work.iddramread_data_type has changed.
# ** Error: (vsim-13) Recompile work.iddramread(structure) because work.iddramread_data_type has changed.
--- Quote End ---

I use the std_logc_2D type (defined in lpm_pack.vhd) a lot and the testbench-writer adds a package at the top of the testbench to define local types for these ports to use while simulating.

Any clue(s)?

Regards,

Josy
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

I ran my first successful ModelSim simulation yesterday (on a lazy Sunday afternoon ...) and you are quite right (as usual) generating repetitive signals is quite easy and very neat.

--- Quote End ---
Glad to hear it!

--- Quote Start ---

I used the native link in QII and that runs fine. Today I decided to continue on the momentum and tried to simulate the other part of the project. So I went through exactly the same motions, copy-paste-edited some of the first testbench into the second. Started the (gate-level) simulation but got this error:
# ** Error: (vsim-13) Recompile work.iddramread because work.iddramread_data_type has changed.# ** Error: (vsim-13) Recompile work.iddramread(structure) because work.iddramread_data_type has changed.

--- Quote End ---
Its not so much an 'error' in the sense of a coding error as it is a dependency error. Modelsim is telling you that you edited and rebuilt a package, but did not then recompile the components that use (depend on) that package.

What is missing in some of these tools is the ability to create a dependency list from .vhd files. Modelsim has a tool called vmake which can create this list from a working design, but I'd really like something that can take a list of .vhd files in a directory and figure out the build order from scratch.

Take a look at vmake to get your dependencies figured out for now.

I'll probably write a Tcl script to figure out dependencies in general, but I won't have time to do that just yet.

If anyone has a .vhd dependency generator, I'd like to hear about it.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Its not so much an 'error' in the sense of a coding error as it is a dependency error. Modelsim is telling you that you edited and rebuilt a package, but did not then recompile the components that use (depend on) that package.
--- Quote End ---

The odd thing is that this 'package' is sitting in the testbench file itself, so I can not see how it would go out of sync.
I did a third project (combining the other two) and that simulated fine with QII0.1SP2 but not with the webversion 11.0SP1. I tried the new VHDL-2008 unconstrained std_logic_vector arrays, but then QII stil generates a xxx_data_type package. And ModelSim chokes on those unconstrained types as well when runnung RTL simulation where it compiles the source code itself, even when I set the 2008 flag. So the only way out may be the 'wide' std_logic_vector but then we might as well start using Verilog ...
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
The odd thing is that this 'package' is sitting in the testbench file itself, so I can not see how it would go out of sync.

--- Quote End ---
Don't forget though that Modelsim keeps a copy of the intermediate build files in subdirectories under 'work'. If you are copying-and-pasting, you are potentially creating duplicates of the same packages. I would expect that'll lead to problems. You should change your mindset to think like a programmer; reusable stuff goes in headers and libraries.

--- Quote Start ---

I did a third project (combining the other two) and that simulated fine with QII0.1SP2 but not with the webversion 11.0SP1.

--- Quote End ---
Simulated? You mean synthesized? Or are you talking about Modelsim ASE that comes with each of these versions?

--- Quote Start ---

I tried the new VHDL-2008 unconstrained std_logic_vector arrays, but then QII stil generates a xxx_data_type package. And ModelSim chokes on those unconstrained types as well when runnung RTL simulation where it compiles the source code itself, even when I set the 2008 flag. So the only way out may be the 'wide' std_logic_vector but then we might as well start using Verilog ...
--- Quote End ---
I haven't run across this particular problem. Why is Quartus generating code? Is this for a post-P&R simulation? Can you post a simplified example?

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Don't forget though that Modelsim keeps a copy of the intermediate build files in subdirectories under 'work'.
--- Quote End ---
I deleted the work directories ... no change

--- Quote Start ---
Simulated? You mean synthesized? Or are you talking about Modelsim ASE that comes with each of these versions?
--- Quote End ---
Gate Level simulation, after P+R. Using the Altera supplied Modelsim executables (ASE).

Actually I tried a small project to see how the Test Bench Writer (11.0sp1) would handle the unconstrained std_logic_vector. I attach a .qar. I included the std_logic_2D version in the .qar for reference.

Regards,

Josy
TP_switch.qar29 KB