Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHi Dave,
--- Quote Start --- I did too. Having to manually create waveforms in the the Max+PlusII simulator led me to start using Modelsim. I guess you were just more patient than me --- Quote End --- I ran my first successful ModelSim simulation yesterday (on a lazy Sunday afternoon ...) and you are quite right (as usual) generating repetitive signals is quite easy and very neat. I used the native link in QII and that runs fine. Today I decided to continue on the momentum and tried to simulate the other part of the project. So I went through exactly the same motions, copy-paste-edited some of the first testbench into the second. Started the (gate-level) simulation but got this error: --- Quote Start --- # ** Error: (vsim-13) Recompile work.iddramread because work.iddramread_data_type has changed. # ** Error: (vsim-13) Recompile work.iddramread(structure) because work.iddramread_data_type has changed. --- Quote End --- I use the std_logc_2D type (defined in lpm_pack.vhd) a lot and the testbench-writer adds a package at the top of the testbench to define local types for these ports to use while simulating. Any clue(s)? Regards, Josy