Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHi Dave,
--- Quote Start --- I suspect that in the regmux code you have library cc_data_types; use cc_data_types.cc_data_types.all; --- Quote End --- Spot on! It is in about every VHDL code I write nowadays. I have another package like that. The idea was to have the 'NativeLink' do it all for me ... (kind of like the 'euthanized' Internal Quartus Simulator where one clicked Run Simulation and waited for the result waveform to show up) Apart from that do you have a clue why I can't get the clock to work, Gate Simulation runs fine, i.e. ModelSim shows a waveform, but I don't see the generated Clk signal toggle at all. Regards, Josy