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The odd thing is that this 'package' is sitting in the testbench file itself, so I can not see how it would go out of sync.
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Don't forget though that Modelsim keeps a copy of the intermediate build files in subdirectories under 'work'. If you are copying-and-pasting, you are potentially creating duplicates of the same packages. I would expect that'll lead to problems. You should change your mindset to think like a programmer; reusable stuff goes in headers and libraries.
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I did a third project (combining the other two) and that simulated fine with QII0.1SP2 but not with the webversion 11.0SP1.
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Simulated? You mean synthesized? Or are you talking about Modelsim ASE that comes with each of these versions?
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I tried the new VHDL-2008 unconstrained std_logic_vector arrays, but then QII stil generates a xxx_data_type package. And ModelSim chokes on those unconstrained types as well when runnung RTL simulation where it compiles the source code itself, even when I set the 2008 flag. So the only way out may be the 'wide' std_logic_vector but then we might as well start using Verilog ...
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I haven't run across this particular problem. Why is Quartus generating code? Is this for a post-P&R simulation? Can you post a simplified example?
Cheers,
Dave
Honored Contributor
