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Don't forget though that Modelsim keeps a copy of the intermediate build files in subdirectories under 'work'.
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I deleted the work directories ... no change
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Simulated? You mean synthesized? Or are you talking about Modelsim ASE that comes with each of these versions?
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Gate Level simulation, after P+R. Using the Altera supplied Modelsim executables (ASE).
Actually I tried a small project to see how the Test Bench Writer (11.0sp1) would handle the unconstrained std_logic_vector. I attach a .qar. I included the std_logic_2D version in the .qar for reference.
Regards,
Josy
Honored Contributor
