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Its not so much an 'error' in the sense of a coding error as it is a dependency error. Modelsim is telling you that you edited and rebuilt a package, but did not then recompile the components that use (depend on) that package.
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The odd thing is that this 'package' is sitting in the testbench file itself, so I can not see how it would go out of sync.
I did a third project (combining the other two) and that simulated fine with QII0.1SP2 but not with the webversion 11.0SP1. I tried the new VHDL-2008 unconstrained std_logic_vector arrays, but then QII stil generates a xxx_data_type package. And ModelSim chokes on those unconstrained types as well when runnung RTL simulation where it compiles the source code itself, even when I set the 2008 flag. So the only way out may be the 'wide' std_logic_vector but then we might as well start using Verilog ...
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