Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHi Josy,
--- Quote Start --- Spot on! It is in about every VHDL code I write nowadays. I have another package like that. --- Quote End --- It is good coding practice to use libraries. Modelsim is nice enough to allow precompiled libraries, so having 'library' code (stuff you do not touch once it is working) compiled into a library is nice, since it you do not need to recompile it. --- Quote Start --- The idea was to have the 'NativeLink' do it all for me ... (kind of like the 'euthanized' Internal Quartus Simulator where one clicked Run Simulation and waited for the result waveform to show up) --- Quote End --- I tend to treat Modelsim and Quartus as completely independent tools, and control each with Tcl scripts. I have never used Nativelink, and am unlikely to try it :) --- Quote Start --- Apart from that do you have a clue why I can't get the clock to work, Gate Simulation runs fine, i.e. ModelSim shows a waveform, but I don't see the generated Clk signal toggle at all. --- Quote End --- What is the variable getting set to? Try adding this code:
assert false
report "Clock half period is " & time'image(TClChClk)
severity note;
Cheers, Dave