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Altera_Forum
Honored Contributor
Honored ContributorMaximum Operating Frequency
Hi everybody,
I designed a sample architecture in Quartus 10.1 by using EP4CE22F17C6. I used a bit generator and parallel mux blocks and run all architectures. I connect output of the bit generator to sel input of the mux blocks. When I added a mux block or removed a mux block, maximum operating freqeuncy of the system changed. I think that this case can not influence maximum operating frequency, because all mux blocks consists of same code and operate parallel. The System's clock name is clk and I write "create_clock -period 0.25 -name clk_100 [get_ports clk]" in SDC file. I atteched my files in this message. I could not solve this problem. Can anyone help me? Thank you very much.15 Replies
Altera_ForumThe max frequncy will change depending on the design, routing and random fitter seed.
Changing the design will change the routing and hence the Fmax- Altera_Forum--- Quote Start --- The max frequncy will change depending on the design, routing and random fitter seed. Changing the design will change the routing and hence the Fmax --- Quote End --- Tricky, thank you for your reply. However, I think that Fmax depends on maximum path delay. In the my design, max. path delay is always fixed. I only change number of parallel mux which consist of same code.
- Altera_Forum
does it really need to code multiplexor as you ?
why not to use simple else clause in single if instead of multiple if , and if you want multiplexor more than for 2 signal it is better to use case. in any case your multiplexor have the same arhitecture and you need only one definition to make instance of all others. Only section for port map should be changed. Are you sure that 0.25 is good value for 100MHz clock??? So you need make code more readable and manageable. And calculate right value. you can apply restructure multiplexor global assignment if it be applicable you will see in report if it takes place. Check Analysis and Synthesis report for average and max LUT-depth keep average at 5 or below. Compare your RTL with structure your await. - Altera_Forum--- Quote Start --- does it really need to code multiplexor as you ? why not to use simple else clause in single if instead of multiple if , and if you want multiplexor more than for 2 signal it is better to use case. in any case your multiplexor have the same arhitecture and you need only one definition to make instance of all others. Only section for port map should be changed. Are you sure that 0.25 is good value for 100MHz clock??? So you need make code more readable and manageable. And calculate right value. you can apply restructure multiplexor global assignment if it be applicable you will see in report if it takes place. Check Analysis and Synthesis report for average and max LUT-depth keep average at 5 or below. Compare your RTL with structure your await. --- Quote End --- Alex96, thank you for your reply. It is important that Fmax is changing when parallel mux blocks are added or removed. Therefore, my aim doesn't design a mux block. My aim is providing of unchanged Fmax for adding or removing of parallel operating blocks. Additionally, I havnt got a 100MHz clock. My period is 0.25. Yes, the code dont manageable, however, more readable and manageable code cant help how change Fmax. The subject isnt manageable or structure of the code, the subject is that Fmax affacts from number of the parallel architecture with same path delay. My architecture is only simple example. Yes, I make a some mistakes, but I couldnt find the problem. I think that I make mistake usage of the tools or Tricky said: random fitter seed. If second is correct, how are there parallel architectures with fixed Fmax?
- Altera_Forum
Start by adding a pll to compensate clock
- Altera_Forum
your clock signal operates at 4GHz according to report and provided value :) and fitter achieved Fmax at 178Mhz in worst-case scenario (Slow 1200mV, 85C).
the worst path in report is yout bit_gen entity. - Altera_Forum--- Quote Start --- Start by adding a pll to compensate clock --- Quote End --- flz47655, thank you for your suggestion. I trid it but, I obtained same results.
- Altera_Forum--- Quote Start --- your clock signal operates at 4GHz according to report and provided value :) and fitter achieved Fmax at 178Mhz in worst-case scenario (Slow 1200mV, 85C). the worst path in report is yout bit_gen entity. --- Quote End --- Alex96, I tried for different frequency values, yet results are same as. For example: create_clock -name "clk_20" -period 10.000ns [get_ports {clk}] -waveform {0.000 5.000}. If the problem is it, I will be very happy to solve my problem :)
- Altera_Forum
Provide real frequency for chip and your task it will exclude undesired Fmax changing)
You can check chip plan how far your instained multiplexors and try to compare when you do muxing in one if for all signals like Out1 := d1&d3&d5 out2 := d2&d4&d6 if sel='0' then out <= out1 else out<=out2 end if I am lazy for semicolons - Altera_Forum--- Quote Start --- Tricky, thank you for your reply. However, I think that Fmax depends on maximum path delay. In the my design, max. path delay is always fixed. I only change number of parallel mux which consist of same code. --- Quote End --- but thats it - the path is not always fixed. When it does the fit, the logic can get put in different places, so the routing delays can vary from build to build - hence the variability.
