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Altera_Forum's avatar
Altera_Forum
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10 years ago

Maximum Operating Frequency

Hi everybody, I designed a sample architecture in Quartus 10.1 by using EP4CE22F17C6. I used a bit generator and parallel mux blocks and run all architectures. I connect output of the bit gener...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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your clock signal operates at 4GHz according to report and provided value :) and fitter achieved Fmax at 178Mhz in worst-case scenario (Slow 1200mV, 85C).

the worst path in report is yout bit_gen entity.

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Alex96,

I tried for different frequency values, yet results are same as. For example: create_clock -name "clk_20" -period 10.000ns [get_ports {clk}] -waveform {0.000 5.000}. If the problem is it, I will be very happy to solve my problem :)