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Honored Contributor
Honored ContributorMaximum Operating Frequency
Hi everybody, I designed a sample architecture in Quartus 10.1 by using EP4CE22F17C6. I used a bit generator and parallel mux blocks and run all architectures. I connect output of the bit gener...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Start by adding a pll to compensate clock --- Quote End --- flz47655, thank you for your suggestion. I trid it but, I obtained same results.
