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Altera_Forum
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10 years ago

Maximum Operating Frequency

Hi everybody, I designed a sample architecture in Quartus 10.1 by using EP4CE22F17C6. I used a bit generator and parallel mux blocks and run all architectures. I connect output of the bit gener...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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Start by adding a pll to compensate clock

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flz47655, thank you for your suggestion. I trid it but, I obtained same results.