Is there a way to optimize VHDL to limit FPGA routing?

What device, what version of Quartus, and how full is it?

Routing goes up by connectivity, i.e. two designs can be the same size, but one is a large-shift register and uses almost no routing, while the other is a large cross-bar(about the worst) and consumes a ton of routing. Designs where "everything talks to everything" tend to stress it. THe other thing is physical issues, like having memory controllers on the top and bottom and having all your logic talk to both, or having transceivers on both sides that talk to everything. This spreads the logic out and uses more routing. LogicLock regions can do the same.

Finally, remember that the router adds delay to meet hold timing. Sometimes incorrect constraints and/or gated clocks cause invalid hold requirements and can cause the router to blow up trying to meet your requirements. Go to assignments -> settings -> fitter and turn off hold optimizations. This may get it to fit, but it will fail hold. Look for anything egregious and see if its correct.

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At the moment I am struggeling with a large design that uses quite a bit of routing on the FPGA.

It is actually so much that it does not fit anymore. Apart from throwing out functionality or memory,

is there a way to optimize VHDL to limit FPGA routing? I have looked at the advanced synthesis cookbook (http://www.altera.com/literature/manual/stx_cookbook.pdf),

but I am not really able to understand what it says other than the compiler takes care of this stuff for you.

I am using the Web edition of Quartus, what can I do to limit the routing?

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is it routing issue or fitting in general. Few points jump to my mind

target optimisation for area

do not over constrain for speed

consider redesign

@Rysc, thanks for the info, it is a bit clearer now. Device is a cyclone IV, Quartus is 14, but I will try with 13.latest as well.

The disign is a microcontroller design, all components (UART, Timers etc.) have their own registers in the entity/component.

The program memory/stack is implemented on-chip. I knew this would give routing problems but I wondered if I could do

something in my codestyle to optimize something. This is a hobby project of mine so the solution get a bigger chip is not

really an option. Would lowering the clock frequency I use help? I have no specific requirements for this. The project is

done purely from an academic point of view.

@kaz, I have tried some of these optimizations and no joy. I have played around with some of these options in a previous

version of my design and found no real changes, But as compilation takes about 24 hours, and I did not write down the

combinations tried so I might not have tried the best combination.

reducing speed is a good option to try it. also any multicycles, false paths may help. gated clock should not done as Rysc indicated.

register packing should be on, try register duplication register retiming on/off.

I'll give that a go. What do you mean by

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also any multicycles, false paths may help.

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?