Is there a way to optimize VHDL to limit FPGA routing?

What device, what version of Quartus, and how full is it?

Routing goes up by connectivity, i.e. two designs can be the same size, but one is a large-shift register and uses almost no routing, while the other is a large cross-bar(about the worst) and consumes a ton of routing. Designs where "everything talks to everything" tend to stress it. THe other thing is physical issues, like having memory controllers on the top and bottom and having all your logic talk to both, or having transceivers on both sides that talk to everything. This spreads the logic out and uses more routing. LogicLock regions can do the same.

Finally, remember that the router adds delay to meet hold timing. Sometimes incorrect constraints and/or gated clocks cause invalid hold requirements and can cause the router to blow up trying to meet your requirements. Go to assignments -> settings -> fitter and turn off hold optimizations. This may get it to fit, but it will fail hold. Look for anything egregious and see if its correct.