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At the moment I am struggeling with a large design that uses quite a bit of routing on the FPGA.
It is actually so much that it does not fit anymore. Apart from throwing out functionality or memory,
is there a way to optimize VHDL to limit FPGA routing? I have looked at the advanced synthesis cookbook (
http://www.altera.com/literature/manual/stx_cookbook.pdf),
but I am not really able to understand what it says other than the compiler takes care of this stuff for you.
I am using the Web edition of Quartus, what can I do to limit the routing?
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is it routing issue or fitting in general. Few points jump to my mind
target optimisation for area
do not over constrain for speed
consider redesign
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