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Altera_Forum
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11 years ago

Is there a way to optimize VHDL to limit FPGA routing?

At the moment I am struggeling with a large design that uses quite a bit of routing on the FPGA. It is actually so much that it does not fit anymore. Apart from throwing out functionality or memor...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

reducing speed is a good option to try it. also any multicycles, false paths may help. gated clock should not done as Rysc indicated.

register packing should be on, try register duplication register retiming on/off.