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Altera_Forum
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11 years ago

Is there a way to optimize VHDL to limit FPGA routing?

At the moment I am struggeling with a large design that uses quite a bit of routing on the FPGA. It is actually so much that it does not fit anymore. Apart from throwing out functionality or memor...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I'll give that a go. What do you mean by

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also any multicycles, false paths may help.

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?