Is there a way to optimize VHDL to limit FPGA routing?

@Rysc, thanks for the info, it is a bit clearer now. Device is a cyclone IV, Quartus is 14, but I will try with 13.latest as well.

The disign is a microcontroller design, all components (UART, Timers etc.) have their own registers in the entity/component.

The program memory/stack is implemented on-chip. I knew this would give routing problems but I wondered if I could do

something in my codestyle to optimize something. This is a hobby project of mine so the solution get a bigger chip is not

really an option. Would lowering the clock frequency I use help? I have no specific requirements for this. The project is

done purely from an academic point of view.

@kaz, I have tried some of these optimizations and no joy. I have played around with some of these options in a previous

version of my design and found no real changes, But as compilation takes about 24 hours, and I did not write down the

combinations tried so I might not have tried the best combination.