if else statement in Verilog

Question

I used to do a lot of C/C++ programming, and I do like to use for loop and if-else statement.

1. I tried to use if-else in Verilog. However, I always got an error which said that --- near text "if", expecting "endmodule". However, if I don't use if-else, everything is fine. The if-else format I used is:

if (a<b) else;

OR:

if(a<b)begin

statements;

end else if (a == b) begin

statements;

end else begin

statements;

end

2. I couldn't assign a value to a variable twice (different values) in verilog. Does people still use loops when it is really needed? For example, to calculate a variable iteratively (say 16 loops) until it converges to its final stable value? Is there an efficient way that a loop is not used to solve problems like this?

Thanks.

altera_forum · Answer

1. Ifs and elseifs should be inside an always or initial block.

2. No, loops are not used like this. Loops unroll into parallel logic, and iteration like that would be more suitable over several clocks.

altera_forum · Answer

What if I need to instantiate a submodule inside if-else statement based on different parameters under if or else? If I can't instantiate a module inside an always block, what is the efficient way to solve such a problem? --- this is similar to call a subroutine with different parameters under if or else.

altera_forum · Answer

Remember, HDL is a description language, not a programming language. You do not "call" a module, its more like placing a chip on a circuit board. A module is instantiated and lasts forever. So modules can only be called inside if-generate setups and the parameters must be static.

altera_forum · Answer

Which means I can't do instantiation of a module in a faked for loop in Verilog, in order to get updated outputs from this instantiation based on the updated inputs to this instantiation. Therefore, wrapping a repeated functionality into a submodule is not a good choice in such a situation.

Besides, it is not a good choice to instantiate a submodule with two tdifferent sets of static parameters in two different situations under if-else statement either. This is because if-else needs to be in an always block and we can't instantiation a submodule in a always block.

Anybody agrees?

altera_forum · Answer

Loop implementation:

if loops are implemented by parallel logic via several clocks, where should the output of loops be stored? Can I feedback the output values back to the input values of the loops at the next posedge of clk? If I do this feedback on the next posedge of clk inside a always block, how should I declare the type of this feedback variable? Does anybody have an example on how a loop should be done in parallel logic? Thanks

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if else statement in Verilog

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