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Altera_Forum
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12 years ago

if else statement in Verilog

I used to do a lot of C/C++ programming, and I do like to use for loop and if-else statement. 1. I tried to use if-else in Verilog. However, I always got an error which said that --- near text ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Remember, HDL is a description language, not a programming language. You do not "call" a module, its more like placing a chip on a circuit board. A module is instantiated and lasts forever. So modules can only be called inside if-generate setups and the parameters must be static.