if else statement in Verilog

Which means I can't do instantiation of a module in a faked for loop in Verilog, in order to get updated outputs from this instantiation based on the updated inputs to this instantiation. Therefore, wrapping a repeated functionality into a submodule is not a good choice in such a situation.

Besides, it is not a good choice to instantiate a submodule with two tdifferent sets of static parameters in two different situations under if-else statement either. This is because if-else needs to be in an always block and we can't instantiation a submodule in a always block.

Anybody agrees?