if else statement in Verilog

Loop implementation:

if loops are implemented by parallel logic via several clocks, where should the output of loops be stored? Can I feedback the output values back to the input values of the loops at the next posedge of clk? If I do this feedback on the next posedge of clk inside a always block, how should I declare the type of this feedback variable? Does anybody have an example on how a loop should be done in parallel logic? Thanks