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Altera_Forum
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12 years ago

if else statement in Verilog

I used to do a lot of C/C++ programming, and I do like to use for loop and if-else statement. 1. I tried to use if-else in Verilog. However, I always got an error which said that --- near text ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

What if I need to instantiate a submodule inside if-else statement based on different parameters under if or else? If I can't instantiate a module inside an always block, what is the efficient way to solve such a problem? --- this is similar to call a subroutine with different parameters under if or else.