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Altera_Forum
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12 years ago

if else statement in Verilog

I used to do a lot of C/C++ programming, and I do like to use for loop and if-else statement. 1. I tried to use if-else in Verilog. However, I always got an error which said that --- near text ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

1. Ifs and elseifs should be inside an always or initial block.

2. No, loops are not used like this. Loops unroll into parallel logic, and iteration like that would be more suitable over several clocks.