How to generate Global RESET signal in Verilog?

You can use an external reset source and then synchronize it inside FPGA. As kaz said internal reset may be OK, but your design can not be put in a safe state when you need it to be.

Thanks kaz!^^

This works too, I've used it for a long time with Altera Cyclone FPGAs. This code assumes CLOCK_50 is running at 50MHz.

    // PowerUP Reset Logic
    // generate a 500ms reset pulse on initial powerup
    reg          pup_count = 25'd0;
    reg         pup_reset = 1'b1;
    always @(posedge CLOCK_50)
        begin
        pup_count <=# TPD pup_count + 1'd1;
        if (pup_count == 25'd25000000) pup_reset <=# TPD 1'b0;
        end
    wire         reset = pup_reset;

    always @(posedge clk or posedge reset)
    begin
    if (reset)
        begin
        run <= 1'b0;
        end
    else
        begin
        run <= mode_normal | mode_emul&stepemul | mode_fast&stepfast | mode_slow&stepslow;
        end
    end

Thanks msj!!!^^

    // PowerUP Reset Logic
    // generate a 500ms reset pulse on initial powerup
    reg          pup_count = 25'd0;
    reg         pup_reset = 1'b1;
    always @(posedge CLOCK_50)
        begin
        pup_count <=# TPD pup_count + 1'd1;
        if (pup_count == 25'd25000000) pup_reset <=# TPD 1'b0;
        end
    wire         reset = pup_reset;

For the design this was used in there was a requirement that the logic be held in reset for at least 500ms at powerup for external hardware to completely stabliize. This was an easy way to accomplish this.

"specify certain values on start" doesn't guarantee a predictable design state after the first clock edge, because the power-on-reset is released asynchronously and might cause timing violations. At worst case, a state machine might fall into a not-recoverable illegal state or a counter start at an unexpected arbitrary value.