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Yes, but that does not matter. Once PUP_RESET gets set to zero it will stay at that value. The only way to set PUP_RESET to one is to powercycle the FPGA and/or reload the configuration file.
So the fact that the counter just keeps on counting and wrapping (forever) is irrelevant.
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Oh, right, I should have seen that myself. I have a follow-up question: why would you want to generate a reset signal on start? Is it just to specify certain values on start? I ask because I thought that was what initial blocks were for. If that assumption is correct, is there a practical difference between using an initial block and a on-start reset signal? Thanks for clearing up my doubts
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