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Honored Contributor
Honored ContributorHow to generate Global RESET signal in Verilog?
Hi, I want to generate a active LOW global reset signal once FPGA device power up. I write my code like this: reg [9:0] reset_sync_n = 1'b0; //initialize the reset signal al...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Yes, but that does not matter. Once PUP_RESET gets set to zero it will stay at that value. The only way to set PUP_RESET to one is to powercycle the FPGA and/or reload the configuration file. So the fact that the counter just keeps on counting and wrapping (forever) is irrelevant. --- Quote End --- Oh, right, I should have seen that myself. I have a follow-up question: why would you want to generate a reset signal on start? Is it just to specify certain values on start? I ask because I thought that was what initial blocks were for. If that assumption is correct, is there a practical difference between using an initial block and a on-start reset signal? Thanks for clearing up my doubts
