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Altera_Forum
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9 years ago

How to generate Global RESET signal in Verilog?

Hi, I want to generate a active LOW global reset signal once FPGA device power up. I write my code like this: reg [9:0] reset_sync_n = 1'b0; //initialize the reset signal al...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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This works too, I've used it for a long time with Altera Cyclone FPGAs. This code assumes CLOCK_50 is running at 50MHz. 

    // PowerUP Reset Logic
    // generate a 500ms reset pulse on initial powerup
    reg          pup_count = 25'd0;
    reg         pup_reset = 1'b1;
    always @(posedge CLOCK_50)
        begin
        pup_count <=# TPD pup_count + 1'd1;
        if (pup_count == 25'd25000000) pup_reset <=# TPD 1'b0;
        end
    wire         reset = pup_reset;

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how exactly does this work? after pup_count saturates won't it wrap around to 25'd0 and then start incrementing again?