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Altera_Forum
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9 years ago

How to generate Global RESET signal in Verilog?

Hi, I want to generate a active LOW global reset signal once FPGA device power up. I write my code like this: reg [9:0] reset_sync_n = 1'b0; //initialize the reset signal al...
Altera_Forum's avatar
Altera_Forum
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9 years ago

You can use an external reset source and then synchronize it inside FPGA. As kaz said internal reset may be OK, but your design can not be put in a safe state when you need it to be.

an external reset signal should pass through a reset synchronizer. There are many documents addressing this issue. Study the followings which discuss this topic in details and present reset synchronizer design & code as well:

http://www.gstitt.ece.ufl.edu/courses/eel4712/labs/cummingssnug2002sj_resets.pdf

http://www.sunburst-design.com/papers/cummingssnug2003boston_resets.pdf

Asynchronous or Synchronous Reset? AS kaz said, an old issue. My conclusion is this:

Use asynchronous design technique in your codes. In the top level, design a reset synchronizer which generates a synchronous reset signal. Connect that synchronized reset signal to your modules. A reset synchronizer should reset asynchronously, and set synchronously.