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Honored Contributor
Honored ContributorHow to generate Global RESET signal in Verilog?
Hi, I want to generate a active LOW global reset signal once FPGA device power up. I write my code like this: reg [9:0] reset_sync_n = 1'b0; //initialize the reset signal al...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- 1. Can the reset_sync_n initialized like the above? Will a active LOW reset signal be generated once FPGA device power up? --- Quote End --- I doubt it as your signal will likely be optimised and set high permanently. --- Quote Start --- 2. What is the right way to generate the RESET signal? --- Quote End --- external reset is recommended. Internally generated reset is not guaranteed though may work well. --- Quote Start --- 3. Asynchronous reset is better or synchronous reset is better? Which one is the better coding practice? --- Quote End --- Old story I am afraid. either way is ok. Altera recommends async (less resource). Xilinx recommends sync (but runs into timing problem). The choice is yours.
