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1. Can the reset_sync_n initialized like the above? Will a active LOW reset signal be generated once FPGA device power up?
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I doubt it as your signal will likely be optimised and set high permanently.
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2. What is the right way to generate the RESET signal?
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external reset is recommended. Internally generated reset is not guaranteed though may work well.
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3. Asynchronous reset is better or synchronous reset is better? Which one is the better coding practice?
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Old story I am afraid. either way is ok. Altera recommends async (less resource). Xilinx recommends sync (but runs into timing problem). The choice is yours.
Honored Contributor
