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Altera_Forum
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9 years ago

How to generate Global RESET signal in Verilog?

Hi, I want to generate a active LOW global reset signal once FPGA device power up. I write my code like this: reg [9:0] reset_sync_n = 1'b0; //initialize the reset signal al...
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Altera_Forum
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9 years ago

"specify certain values on start" doesn't guarantee a predictable design state after the first clock edge, because the power-on-reset is released asynchronously and might cause timing violations. At worst case, a state machine might fall into a not-recoverable illegal state or a counter start at an unexpected arbitrary value.

That's why you want a system wide reset that is synchronously released after the design clock is stable.