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Honored Contributor
Honored ContributorHow to generate Global RESET signal in Verilog?
Hi, I want to generate a active LOW global reset signal once FPGA device power up. I write my code like this: reg [9:0] reset_sync_n = 1'b0; //initialize the reset signal al...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- how exactly does this work? after pup_count saturates won't it wrap around to 25'd0 and then start incrementing again? --- Quote End --- Yes, but that does not matter. Once PUP_RESET gets set to zero it will stay at that value. The only way to set PUP_RESET to one is to powercycle the FPGA and/or reload the configuration file. So the fact that the counter just keeps on counting and wrapping (forever) is irrelevant.
