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Altera_Forum
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9 years ago

How to generate Global RESET signal in Verilog?

Hi, I want to generate a active LOW global reset signal once FPGA device power up. I write my code like this: reg [9:0] reset_sync_n = 1'b0; //initialize the reset signal al...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

For the design this was used in there was a requirement that the logic be held in reset for at least 500ms at powerup for external hardware to completely stabliize. This was an easy way to accomplish this.