I've got a decimator block written in Verilog. It's the standard structure: flops, then constant multiplication, then an accumulate tree. However, Quartus is using the DSP blocks for the multiplies and then failing timing specs. This seems like an early stage problem as it starts consuming DSP resources right at the early portions of Analysis & Synthesis. Is there a way to make Quartus synthesize those constant multiplies short of rewriting the block with shifts and adds by hand? I'm on Quartus 12.1sp1 on Windows 7 64-bit. Thanks.

I dont quite get what the problem is? DSP blocks are the fastest way to do multiplies on the chip. So why would you not want to use them. Sometime you can have problmes routing into or out of a DSP block, but the solution for that is add more pipeline registers around the multiplier so that it allows the fitter to shorten the distance between stages and can put a register right next to the multiplier.

PS. Ive only had problems with the above when setting the clock speed to >350MHz on a stratix 4 and 5.

--- Quote Start --- I dont quite get what the problem is? DSP blocks are the fastest way to do multiplies on the chip. So why would you not want to use them. --- Quote End --- That's true if both inputs are variables. However, when one side is a constant using the multiplier is probably the slowest. For example, 30*X would be DRAMATICALLY faster being done as 32*X - 2*X. A multiplier can't even get close.

True, but you'll have to work that out for yourself. Afaik, the synthesisor cannot work out the 2^n constants itself. The example would also fall down and get complicated as the constant values get larger and larger. Your example is very simple and just requires a single adder. As the constants get to values requiring 10s or 100s of adders, a DSP block might be easier.

--- Quote Start --- True, but you'll have to work that out for yourself. Afaik, the synthesisor cannot work out the 2^n constants itself. The example would also fall down and get complicated as the constant values get larger and larger. Your example is very simple and just requires a single adder. As the constants get to values requiring 10s or 100s of adders, a DSP block might be easier. --- Quote End --- You can get almost every constant out to 16 bits with right around 5 operations if you allow subtractions. I'm really surprised that the tools can't work out these constants. Even the low-end ASIC synthesis tools have been able to do this kind of thing for quite a few years. Sigh. I guess I have to create some code to solve the knapsack problem and generate verilog. Again. Thanks for the advice.

How to force Quartus to synthesize constant mutiplies

20 Replies

Altera_Forum
Honored Contributor
12 years ago
I dont quite get what the problem is? DSP blocks are the fastest way to do multiplies on the chip. So why would you not want to use them. Sometime you can have problmes routing into or out of a DSP block, but the solution for that is add more pipeline registers around the multiplier so that it allows the fitter to shorten the distance between stages and can put a register right next to the multiplier.
Altera_Forum
Honored Contributor
12 years ago
PS. Ive only had problems with the above when setting the clock speed to >350MHz on a stratix 4 and 5.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
I dont quite get what the problem is? DSP blocks are the fastest way to do multiplies on the chip. So why would you not want to use them.
--- Quote End ---

That's true if both inputs are variables. However, when one side is a constant using the multiplier is probably the slowest. For example, 30*X would be DRAMATICALLY faster being done as 32*X - 2*X. A multiplier can't even get close.
Altera_Forum
Honored Contributor
12 years ago
True, but you'll have to work that out for yourself. Afaik, the synthesisor cannot work out the 2^n constants itself. The example would also fall down and get complicated as the constant values get larger and larger. Your example is very simple and just requires a single adder. As the constants get to values requiring 10s or 100s of adders, a DSP block might be easier.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
True, but you'll have to work that out for yourself. Afaik, the synthesisor cannot work out the 2^n constants itself. The example would also fall down and get complicated as the constant values get larger and larger. Your example is very simple and just requires a single adder. As the constants get to values requiring 10s or 100s of adders, a DSP block might be easier.
--- Quote End ---

You can get almost every constant out to 16 bits with right around 5 operations if you allow subtractions.

I'm really surprised that the tools can't work out these constants. Even the low-end ASIC synthesis tools have been able to do this kind of thing for quite a few years.

Sigh. I guess I have to create some code to solve the knapsack problem and generate verilog. Again.

Thanks for the advice.
Altera_Forum
Honored Contributor
12 years ago
It might be worth raising a support request for this as I can see the benefit.
Altera_Forum
Honored Contributor
12 years ago
I presume you know that you can always enforce multiplier implementation in logic cells on an entity or signal level by a multstyle synthesis attribute. Does it solve the timing problem?
Altera_Forum
Honored Contributor
12 years ago
The original post is about not using multipliers but using shift. One input is constant and so may be convertable to sum or difference of power of 2. As far as I Know the tool does not do this sort of conversion.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
The original post is about not using multipliers but using shift. One input is constant and so may be convertable to sum or difference of power of 2. As far as I Know the tool does not do this sort of conversion.
--- Quote End ---

Shift and add is the way how the synthesis tool does implement a multiplier without DSP blocks. In so far multstyle = "logic" does use it. But there's no point in design synthesis where you'll see explicite adders or shift registers, because everything is translated to logic elements.

The question is of course, if the synthesis tool implements the defined function effectively, but the problem isn't specific to constant multipliers. I'm under the impression that Quartus is quite good in implementing arithmetic. It has some obvious weaknesses in implementing non-arithmetic problems in arithmetic mode of logic elements.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
Shift and add is the way how the synthesis tool does implement a multiplier without DSP blocks. In so far multstyle = "logic" does use it. But there's no point in design synthesis where you'll see explicite adders or shift registers, because everything is translated to logic elements.

The question is of course, if the synthesis tool implements the defined function effectively, but the problem isn't specific to constant multipliers. I'm under the impression that Quartus is quite good in implementing arithmetic. It has some obvious weaknesses in implementing non-arithmetic problems in arithmetic mode of logic elements.
--- Quote End ---

Multipliers implemented in logic are full mults that support two variable inputs. I don’t know how they are implemented exactly in FPGAs but from per-FPGA era(Logic Design by Charles Roth) it was based on shift/add/control in an elaborate design.

However, if one input is constant we don’t need that apart from shift only(or plus adder). So the two cases are distinct from design perspective. The original post is not obbssesed with shift but wants simplified design.

Personally I prefer DSP blocks. I might target one or so coeffs (say) as power of 2 to save few mults just in case.

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How to force Quartus to synthesize constant mutiplies

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