--- Quote Start ---
True, but you'll have to work that out for yourself. Afaik, the synthesisor cannot work out the 2^n constants itself. The example would also fall down and get complicated as the constant values get larger and larger. Your example is very simple and just requires a single adder. As the constants get to values requiring 10s or 100s of adders, a DSP block might be easier.
--- Quote End ---
You can get almost every constant out to 16 bits with right around 5 operations if you allow subtractions.
I'm really surprised that the tools can't work out these constants. Even the low-end ASIC synthesis tools have been able to do this kind of thing for quite a few years.
Sigh. I guess I have to create some code to solve the knapsack problem and generate verilog. Again.
Thanks for the advice.
Honored Contributor
