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Altera_Forum
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12 years ago

How to force Quartus to synthesize constant mutiplies

I've got a decimator block written in Verilog. It's the standard structure: flops, then constant multiplication, then an accumulate tree. However, Quartus is using the DSP blocks for the multi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

True, but you'll have to work that out for yourself. Afaik, the synthesisor cannot work out the 2^n constants itself. The example would also fall down and get complicated as the constant values get larger and larger. Your example is very simple and just requires a single adder. As the constants get to values requiring 10s or 100s of adders, a DSP block might be easier.