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Altera_Forum
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12 years ago

How to force Quartus to synthesize constant mutiplies

I've got a decimator block written in Verilog. It's the standard structure: flops, then constant multiplication, then an accumulate tree. However, Quartus is using the DSP blocks for the multi...
Altera_Forum's avatar
Altera_Forum
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12 years ago

The original post is about not using multipliers but using shift. One input is constant and so may be convertable to sum or difference of power of 2. As far as I Know the tool does not do this sort of conversion.