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Altera_Forum's avatar
Altera_Forum
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12 years ago

How to force Quartus to synthesize constant mutiplies

I've got a decimator block written in Verilog. It's the standard structure: flops, then constant multiplication, then an accumulate tree. However, Quartus is using the DSP blocks for the multi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I dont quite get what the problem is? DSP blocks are the fastest way to do multiplies on the chip. So why would you not want to use them. Sometime you can have problmes routing into or out of a DSP block, but the solution for that is add more pipeline registers around the multiplier so that it allows the fitter to shorten the distance between stages and can put a register right next to the multiplier.