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Altera_Forum's avatar
Altera_Forum
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12 years ago

How to force Quartus to synthesize constant mutiplies

I've got a decimator block written in Verilog. It's the standard structure: flops, then constant multiplication, then an accumulate tree. However, Quartus is using the DSP blocks for the multi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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I dont quite get what the problem is? DSP blocks are the fastest way to do multiplies on the chip. So why would you not want to use them.

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That's true if both inputs are variables. However, when one side is a constant using the multiplier is probably the slowest. For example, 30*X would be DRAMATICALLY faster being done as 32*X - 2*X. A multiplier can't even get close.