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Shift and add is the way how the synthesis tool does implement a multiplier without DSP blocks. In so far multstyle = "logic" does use it. But there's no point in design synthesis where you'll see explicite adders or shift registers, because everything is translated to logic elements.
The question is of course, if the synthesis tool implements the defined function effectively, but the problem isn't specific to constant multipliers. I'm under the impression that Quartus is quite good in implementing arithmetic. It has some obvious weaknesses in implementing non-arithmetic problems in arithmetic mode of logic elements.
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Multipliers implemented in logic are full mults that support two variable inputs. I don’t know how they are implemented exactly in FPGAs but from per-FPGA era(Logic Design by Charles Roth) it was based on shift/add/control in an elaborate design.
However, if one input is constant we don’t need that apart from shift only(or plus adder). So the two cases are distinct from design perspective. The original post is not obbssesed with shift but wants simplified design.
Personally I prefer DSP blocks. I might target one or so coeffs (say) as power of 2 to save few mults just in case.
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