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New ContributorHow can you create a .vqm file or equivalent in Quartus Prime Standard 23.1?
I am trying to send my design without sending the source HDL design files, and I have been able to create a .vo file, but that is only used for simulation. I want to be able to synthesize and compile a new design that incorporates my exported design.
I have tried using the quartus_eda tcl command, but I get errors when I try to invoke it in any way other than through the gui.
Most of the support that I have seen targets Quartus Prime Pro version, but the device that I am targeting (Cyclone IV) is not supported in Quartus Prime Pro.
Any help would be greatly appreciated.
If I understand correctly, you want to share your design without giving the source file. Which is why you want to create the .vqm. Let me know if my understanding is incorrect?
Is that fine for you to exploring export partition instead? https://www.intel.com/content/www/us/en/docs/programmable/683475/19-4/exporting-compilation-results.html
Otherwise, you will need the synplify pro as describe in
16 Replies
KennyT_alteraSuper Contributor
Do you have the original verilog/vhdl design in Quartus Prime Standard 23.1? Or this .vqm file is converted from third party tools?
IwtiI have the original verilog design in Quartus Prime Standard 23.1.
I want to generate a .vqm from my design.- KennyT_altera
If I understand correctly, you want to share your design without giving the source file. Which is why you want to create the .vqm. Let me know if my understanding is incorrect?
Is that fine for you to exploring export partition instead? https://www.intel.com/content/www/us/en/docs/programmable/683475/19-4/exporting-compilation-results.html
Otherwise, you will need the synplify pro as describe in
- KennyT_altera
Is there any update base on the question above?
- Iwti
Yes, that is correct.
I am trying the design partition flow first.
I have exported the top level design partition, but I am having issues integrating it into another test project.
In another project, I have a top-level wrapper with the same I/O ports, but the tool does not allow me to import a design partition to that module. So, I made an empty submodule with the same I/O ports (black box) and I was able to successfully import the design partition.
Is this the correct flow?
Another question:
I am using Quartus Prime Standard, but if the target project that I am sharing the design without giving the source file is Quartus Lite, then is exporting a .vqm file the only option?
- KennyT_altera
Firstly, quartus lite does not support design partition. You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pdf
Yes, your flow is correct for integrating a design partition:
- You must instantiate a black box (empty submodule with matching ports/parameters) in the target project to import the partition, we call that as stub.
- The tool does not allow importing a partition directly to a top-level module; it must be a submodule/instance with the same interface https://www.intel.com/content/www/us/en/docs/programmable/683796/18-1/creating-black-boxes-in-verilog-hdl-81234.html
- The black box approach is required because the partition import mechanism expects a matching instance in the hierarchy, not the top-level entity
- KennyT_altera
Do you have further question? If no, we shall close this thead.
- Iwti
I am still running into an issue with integrating a the partition into another project.
I have tried the flow locally (instantiating a stub, and then adding a design partition to the target hierarchy level, in this case the top level wrapper) on a test project and it worked without issue.
However, when sharing the design partition externally, I see the following errors:
1. Error: 292014 Can't find valid feature line for core in current license
2. Error: 137004 Can't parse file E:/import/FPGA_Top.map.hdbx -- line 1 contains syntax error "
How can the flow work locally, and not externally?
Is there a setting that I am missing for properly exporting the license for IP within my design?
- KennyT_altera
Since the error is complaining about license, do you know if you already have full subscription license? If that fine to take a screenshots of it, tools -> license setup?
- Iwti
Yes, I have the full version, and so does the external vendor.
The issue appears to be with a license that is used for some encrypted IP within our design.
Is the project that is importing the design partition also required to have this license, even though the partition has already been synthesized?I unfortunately cannot share the screenshot.
- KennyT_altera
If a design partition (.qdb) contains encrypted IP, the project importing it must also have a valid license for that IP, even if the partition was already synthesized. This is because Quartus performs license checks during later stages like fitting and assembly, not just during synthesis. Without the proper license, the IP may be flagged as "Unlicensed," which can lead to errors or limited functionality.
To prevent issues, ensure that all required IP licenses are available in the importing environment. You can verify license status through the Assembler report or use Intel’s License Assistant for troubleshooting.
- Iwti
I see, then it looks like this flow will not work for me since the external vendor is merely testing the FPGA DUT and as such does not have access to the required IP license.
Does generating a .vqm file from synplify pro have this same limitation?
- KennyT_altera
I believe this issue occurs whenever a license from a third-party vendor is involved. However, without testing it in Synplify Pro VQM, we can’t be completely certain.
- KennyT_altera
Not sure if you have further question today?
- Iwti
No further questions, the .vqm file was able to be compiled without any license issues.
Thanks!
