Forum Discussion
Iwti
New Contributor
New ContributorHow can you create a .vqm file or equivalent in Quartus Prime Standard 23.1?
I am trying to send my design without sending the source HDL design files, and I have been able to create a .vo file, but that is only used for simulation. I want to be able to synthesize and compile...
If I understand correctly, you want to share your design without giving the source file. Which is why you want to create the .vqm. Let me know if my understanding is incorrect?
Is that fine for you to exploring export partition instead? https://www.intel.com/content/www/us/en/docs/programmable/683475/19-4/exporting-compilation-results.html
Otherwise, you will need the synplify pro as describe in
KennyT_altera
Super Contributor
Super ContributorDo you have the original verilog/vhdl design in Quartus Prime Standard 23.1? Or this .vqm file is converted from third party tools?
