Forum Discussion
New ContributorHow can you create a .vqm file or equivalent in Quartus Prime Standard 23.1?
If I understand correctly, you want to share your design without giving the source file. Which is why you want to create the .vqm. Let me know if my understanding is incorrect?
Is that fine for you to exploring export partition instead? https://www.intel.com/content/www/us/en/docs/programmable/683475/19-4/exporting-compilation-results.html
Otherwise, you will need the synplify pro as describe in
Super ContributorFirstly, quartus lite does not support design partition. You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pdf
Yes, your flow is correct for integrating a design partition:
- You must instantiate a black box (empty submodule with matching ports/parameters) in the target project to import the partition, we call that as stub.
- The tool does not allow importing a partition directly to a top-level module; it must be a submodule/instance with the same interface https://www.intel.com/content/www/us/en/docs/programmable/683796/18-1/creating-black-boxes-in-verilog-hdl-81234.html
- The black box approach is required because the partition import mechanism expects a matching instance in the hierarchy, not the top-level entity
