Hierarchical reference to custom type

I normally do that by getting copy of state value as output from design

For hierarchical approach One can use signal spy. Here is an example I did years ago if it still applies! but I don't remember detailsed explanation

--Signal spy:
Library modelsim_lib;
Use modelsim_lib.util.all;
constant test_path   : string := "/my_tb/u1/adder1/"; -- path of modelsim units
signal spy_dout     : std_logic_vector (15 downto 0);         
signal spy_clk      : std_logic;
...
--spy port mapping
process
begin
   init_signal_spy(test_path & "result", "spy_dout",1);
   init_signal_spy(test_path & "clock", "spy_clk",1);
   wait;
end process;

What is the error? You will need to have SM_STATES type declared in a package so that you can see it in the testbench (Im not sure if you can use hierarchical references to fetch types outside of packages).

Ive just looked it up - external names can only fetch constants, shared variables and signals. So you need to make the type declaration visible by putting it in a package.

package magic_comms is
    signal copy_of_current_state : work.pkg_my_package.SM_STATES;
    ... other signals here if you want
end package magic_comms;
...
use work.magic_comms.all;
architecture rtl of my_design is
begin
    copy_of_current_state <= current_state;
    ... Other code, like the state machine that sets current_state
end rtl;
...
-- In the testbench
use work.magic_comms.all;
architecture rtl of my_testbench is
begin
    process(all)
    begin
        wait until copy_of_current_state=state4;
        ...
    end process;
end rtl;

Thanks Tricky - I guess I'll go the package route.