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In my testbench, I want to wait until this state machine has reached a certain state before allowing the test sequence to continue.
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This is a red flag that you're not writing a proper testbench. In the real world, signals can only interact with other signals that are available on the interface. If you need to dive down into the design in order for the testbench to work, then you're not modelling how the system will actually work...which is kind of the whole point of a testbench.
Having said that, there are cases where it is handy to short circuit reality and make the internals visible to the testbench. A simple way is to define a package and put a copy of your signals in the package.
package magic_comms is
signal copy_of_current_state : work.pkg_my_package.SM_STATES;
... other signals here if you want
end package magic_comms;
...
use work.magic_comms.all;
architecture rtl of my_design is
begin
copy_of_current_state <= current_state;
... Other code, like the state machine that sets current_state
end rtl;
...
-- In the testbench
use work.magic_comms.all;
architecture rtl of my_testbench is
begin
process(all)
begin
wait until copy_of_current_state=state4;
...
end process;
end rtl;
Kevin Jennings
Honored Contributor
