Hierarchical reference to custom type

For hierarchical approach One can use signal spy. Here is an example I did years ago if it still applies! but I don't remember detailsed explanation

--Signal spy:
Library modelsim_lib;
Use modelsim_lib.util.all;
constant test_path   : string := "/my_tb/u1/adder1/"; -- path of modelsim units
signal spy_dout     : std_logic_vector (15 downto 0);         
signal spy_clk      : std_logic;
...
--spy port mapping
process
begin
   init_signal_spy(test_path & "result", "spy_dout",1);
   init_signal_spy(test_path & "clock", "spy_clk",1);
   wait;
end process;