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Altera_Forum
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9 years ago

Hierarchical reference to custom type

I have a state machine defined with the following lines in one of my source files: type SM_STATES is (idle, state1, state2, state3, state4); signal current_state : SM_STATES; In my testbenc...
Altera_Forum's avatar
Altera_Forum
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9 years ago

What is the error? You will need to have SM_STATES type declared in a package so that you can see it in the testbench (Im not sure if you can use hierarchical references to fetch types outside of packages).

@Kaz - Signal spy is mentor's way of allowing hierarchical referencing in VHDL pre-2008. With VHDL 2008 you shouldnt need signal spy any more.