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Altera_Forum
Honored Contributor
Honored ContributorHierarchical reference to custom type
I have a state machine defined with the following lines in one of my source files: type SM_STATES is (idle, state1, state2, state3, state4); signal current_state : SM_STATES; In my testbenc...
Altera_ForumHonored Contributor
Honored ContributorI normally do that by getting copy of state value as output from design
