Help needed in VHDL Testbench

This will be because you have the same assertion error if sel_s is '0' or '1' - so I assume it's going to happen on every clock cycle that enable_i is set.

@tricky,

Sorry, I missread the code - But you still have the same error reported for two different assertions. maybe you should change the text so that it is clearer which one is firing then you can use the wave window to debug the problem..

@tricky,

wait for 10 ns;	
    reset_n_i <= '1';
    wait for 15 ns;
    enable_i <= '1';
    phi_e_i <= "101010101111010101101010101101010101"; 
    thresh_i <= "10000000";
    
    wait for 10 ns;
    phi_e_i <= "111010101101010101010101010101010101";
    thresh_i <= "00010110";
    
    wait for 10 ns;
    phi_e_i <= "100000000000000000010101010101010101";
    thresh_i <= "00010101";
    
	 wait for 20 ns;
	 phi_e_i <= "110101010101010101010101111110101010";
	 thresh_i <= "01110000";
	  
    wait for 15 ns;
    phi_e_i <= "000000000000000000000000001010110101";
    thresh_i <= "01111111";
	 
    wait for 1 ms;
    reset_n_i <= '0';
  
    wait for 1 ms;
    reset_n_i <= '1';
    wait for 1 ms;
    enable_i <= '0';
    wait for 1 ms;
    enable_i <= '1';
    wait for 1 ms;
    assert False report "End simulation!" severity Failure;
  end process;
  delay_rst_s <= reset_n_i after 1 ns;
  new_thresh_s <= std_logic_vector(thresh_i & "0000000000000000000000000000");
  p_check_outp: process(delay_rst_s, clk_128meg_i)
  begin
    if (delay_rst_s = '0') then
      old_phi_e_s <= (others => '0');
      assert phi_e_gr_o = "000000000000000000000000000000000000" report "Output not set to default value when reset_n_i= 0" severity error;
    elsif (clk_128meg_i'event and clk_128meg_i = '0')then
      if (enable_i = '1') then
         old_phi_e_s <= phi_e_i;
        if (abs(signed(phi_e_i) - signed(old_phi_e_s)) >= to_integer(unsigned(new_thresh_s))) then
          assert phi_e_gr_o = old_phi_e_s report "Wrong output: phi_e_gr_o should be equal to old phi_e_i" severity error;
        elsif (abs(signed(phi_e_i) - signed(old_phi_e_s)) < to_integer(unsigned(new_thresh_s))) then
          assert phi_e_gr_o = phi_e_i report "Wrong output: phi_e_gr_o should be equal to phi_e_i" severity error; 
        end if;
	  else
         old_phi_e_s <= (others => '0');
         assert phi_e_gr_o = "000000000000000000000000000000000000" report " Output not set to default value when enable_i= 0" severity error;
      end if;
    end if;
  end process;

This is debugging.

Hello all,

I dont understand your question? Is it about naming scope in VHDL? Names can be re-used in as many files as long as you dont manage to put the same name twice in the same scope.

Ok, i will post an example , I am just writing the entity and the portmap. I hope so this would be enough for you to have an idea of what I trying to ask.

entity tdc_decode is
    port (reset_n_i      : in std_logic;      --asynch reset
          clk_128meg_i   : in std_logic;   --128 meg system clock
      enable_i       : in std_logic;   -- enable signal
      tdc_i          : in std_logic_vector(63 downto 0);    -- tdc data
      rise_o         : out std_logic_vector(5 downto 0);    -- value for rise
      rise_fall_o    : out std_logic_vector(6 downto 0));  -- rise - fall value
end tdc_decode;

  uut: tdc_decode
  port map (reset_n_i => reset_n_i,
            clk_128meg_i => clk_128meg_i,
            enable_i => enable_i,
            tdc_i => tdc_i,
            rise_o => rise_o,
            rise_fall_o => rise_fall_o
           );

entity tdc_readout is
    port (reset_n_i : in std_logic;
      enable_i : in std_logic;
      clk_128meg_i : in std_logic;
      tdc_i : in std_logic_vector(63 downto 0);         --tdc data
      scale_i : in std_logic_vector(7 downto 0);        --scaling value from spi reg
      rise_fall_o : out std_logic_vector(6 downto 0);   --calculated rise fall value to spi
      phi_frac_o : out std_logic_vector(13 downto 0));  --phi fractional value to add3
end tdc_readout;

i_tdc_decode : tdc_decode
  port map (reset_n_i       => reset_n_i,      -- reset from pad
            clk_128meg_i    => clk_128meg_i,   -- system clock
            enable_i        => enable_i,
        tdc_i           => tdc_reg_s,
        rise_o          => rise_s,
        rise_fall_o     => rise_fall_o);   

To your information, I have added the source files tdc_readout, tdc_decode and only the testbench tb_tdc_readout to my simulation

Your question is still not clear, can you please post some code that shows an error?