Help needed in VHDL Testbench

@tricky,

I have tried all possibilities and I find that the old_phi_e_s is not pushed to phi_e_gr_o as well as phi_e_i is not pushed to phi_e_gr_o. This is the waveform I obtain when I run the simulation.

https://www.alteraforum.com/forum/attachment.php?attachmentid=12710

Also I have changed my testbench because there was a kind of mistake in the design. This is my testbench code:

wait for 10 ns;	
    reset_n_i <= '1';
    wait for 15 ns;
    enable_i <= '1';
    phi_e_i <= "101010101111010101101010101101010101"; 
    thresh_i <= "10000000";
    
    wait for 10 ns;
    phi_e_i <= "111010101101010101010101010101010101";
    thresh_i <= "00010110";
    
    wait for 10 ns;
    phi_e_i <= "100000000000000000010101010101010101";
    thresh_i <= "00010101";
    
	 wait for 20 ns;
	 phi_e_i <= "110101010101010101010101111110101010";
	 thresh_i <= "01110000";
	  
    wait for 15 ns;
    phi_e_i <= "000000000000000000000000001010110101";
    thresh_i <= "01111111";
	 
    wait for 1 ms;
    reset_n_i <= '0';
  
    wait for 1 ms;
    reset_n_i <= '1';
    wait for 1 ms;
    enable_i <= '0';
    wait for 1 ms;
    enable_i <= '1';
    wait for 1 ms;
    assert False report "End simulation!" severity Failure;
  end process;
  delay_rst_s <= reset_n_i after 1 ns;
  new_thresh_s <= std_logic_vector(thresh_i & "0000000000000000000000000000");
  p_check_outp: process(delay_rst_s, clk_128meg_i)
  begin
    if (delay_rst_s = '0') then
      old_phi_e_s <= (others => '0');
      assert phi_e_gr_o = "000000000000000000000000000000000000" report "Output not set to default value when reset_n_i= 0" severity error;
    elsif (clk_128meg_i'event and clk_128meg_i = '0')then
      if (enable_i = '1') then
         old_phi_e_s <= phi_e_i;
        if (abs(signed(phi_e_i) - signed(old_phi_e_s)) >= to_integer(unsigned(new_thresh_s))) then
          assert phi_e_gr_o = old_phi_e_s report "Wrong output: phi_e_gr_o should be equal to old phi_e_i" severity error;
        elsif (abs(signed(phi_e_i) - signed(old_phi_e_s)) < to_integer(unsigned(new_thresh_s))) then
          assert phi_e_gr_o = phi_e_i report "Wrong output: phi_e_gr_o should be equal to phi_e_i" severity error; 
        end if;
	  else
         old_phi_e_s <= (others => '0');
         assert phi_e_gr_o = "000000000000000000000000000000000000" report " Output not set to default value when enable_i= 0" severity error;
      end if;
    end if;
  end process;

.

Please help me to solve this issue. I am really fed up of why I am not getting the output