Forum Discussion
Altera_Forum
Honored Contributor
9 years agoOk, i will post an example , I am just writing the entity and the portmap. I hope so this would be enough for you to have an idea of what I trying to ask.
Consider this as the first source code , Consider the output port rise_oentity tdc_decode is
port (reset_n_i : in std_logic; --asynch reset
clk_128meg_i : in std_logic; --128 meg system clock
enable_i : in std_logic; -- enable signal
tdc_i : in std_logic_vector(63 downto 0); -- tdc data
rise_o : out std_logic_vector(5 downto 0); -- value for rise
rise_fall_o : out std_logic_vector(6 downto 0)); -- rise - fall value
end tdc_decode;
The testbench (port mapping section) for this source code is as follows:
uut: tdc_decode
port map (reset_n_i => reset_n_i,
clk_128meg_i => clk_128meg_i,
enable_i => enable_i,
tdc_i => tdc_i,
rise_o => rise_o,
rise_fall_o => rise_fall_o
);
This is the second source code tdc_readout entity tdc_readout is
port (reset_n_i : in std_logic;
enable_i : in std_logic;
clk_128meg_i : in std_logic;
tdc_i : in std_logic_vector(63 downto 0); --tdc data
scale_i : in std_logic_vector(7 downto 0); --scaling value from spi reg
rise_fall_o : out std_logic_vector(6 downto 0); --calculated rise fall value to spi
phi_frac_o : out std_logic_vector(13 downto 0)); --phi fractional value to add3
end tdc_readout; However,I am going to port map the inputs of tdc_decode in tdc_readout: i_tdc_decode : tdc_decode
port map (reset_n_i => reset_n_i, -- reset from pad
clk_128meg_i => clk_128meg_i, -- system clock
enable_i => enable_i,
tdc_i => tdc_reg_s,
rise_o => rise_s,
rise_fall_o => rise_fall_o); Now, what I need is to use the output port "rise_o values " which I calculated in tdc_decode in my next testbench that I have written for tdc_readout (i.e. tb_tdc_readout). How can I do that. Was I clear?