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Altera_Forum
Honored Contributor
Honored ContributorHelp needed in VHDL Testbench
Hi all, I have written the testbench file in such a manner that I need to perform updowncounting and downcounting based on the value of dir_s. But the problem is, when I execute the code, the di...
Altera_ForumHonored Contributor
Honored ContributorI dont understand your question? Is it about naming scope in VHDL? Names can be re-used in as many files as long as you dont manage to put the same name twice in the same scope.
Why not post an example with the problem you're having?
