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Altera_Forum
Honored Contributor
Honored ContributorHelp needed in VHDL Testbench
Hi all, I have written the testbench file in such a manner that I need to perform updowncounting and downcounting based on the value of dir_s. But the problem is, when I execute the code, the di...
Altera_ForumHonored Contributor
Honored ContributorThis is debugging.
I have no knowledge of your deisgn and you are the best person to fix it. Use the testbench and internal wave forms to trace a known input through the design, and ensure it is the correct values at all stages through the design.
